Electronic systems are often synchronous or clocked. These systems may rely on accurate clocks to synchronize the timing of operations and data transfers. A crystal oscillator can be used to generate a clock at a base frequency, which is then divided or multiplied to create one or more clocks with desired frequencies. An external clock can be received and likewise divided or multiplied to produce internal clocks.
Clocks are sometimes generated from oscillator outputs using phase-locked loops (PLL's). PLLs are one of the most widely used building blocks in digital systems today. FIG. 1 illustrates a typical PLL. Phase detector 10 receives a reference-clock input IN from an external oscillator or clock source. The phase and frequency of the reference clock IN is compared to the phase and frequency of a feedback clock FB generated by voltage-controlled oscillator (VCO) 14. The feedback clock can be the output clock generated by the PLL, or a divided-down derivative of the output clock from VCO 14 such as produced by feedback counter 16.
Phase detector 10 outputs up and down signals UP, DN when the phase or frequency of one input does not match the phase or frequency of the other input. These up and down signals cause charge pump 12 to add or remove charge from filter capacitor 20, which integrates the charge. As charge is added or removed through resistor 21 from filter capacitor 20, the voltage input VCTL to VCO 14 is increased or decreased. VCO 14 responds by increasing or decreasing the frequency of the output clock. The feedback clock to phase detector 10 through counter 16 is likewise changed by VCO 14.
As charge pump 12 adds or removes charge from filter capacitor 20, altering control voltage VCTL input to VCO 14, the phase and frequency of the feedback clock are adjusted until the reference clock is matched. Then phase detector 10 stops generating up and down signals to charge pump 12, until charge leaks off filter capacitor 20 or the reference clock changes.
FIG. 2 is a timing diagram of clock, such as input IN to a PLL. The duty cycle of the clock may not be exactly 50%-50%. The high pulse width TH is shorter than the low pulse width TL in this example. The resulting duty cycle is about 30-70 rather than the more ideal 50-50.
Some systems are quite sensitive to the duty cycle of a clock. System chips and microprocessors may require the duty cycle to be within 5% of 50-50. When the high or low pulse width is too short, internal logic such as registers may fail to fully flip logic states, resulting in logical errors or other failures.
The output clock of a PLL could be used to correct a duty cycle of an input clock that is not 50-50. However, a PLL may introduce noise or phase errors into its output or feedback clock. Thus the quality of a PLL's output or feedback clock is not as good as its input clock.
What is desired is a PLL that can be used to correct clock duty cycles. A duty cycle correcting circuit that uses a PLL but still produces a duty-cycle-corrected clock that has the good noise profile of an input clock is desirable.